Photonics
& Roadmapping Spring Conference
May
3-4, 2004
This conference will be an opportunity to:
- Hear from MIT faculty on new directions in photonics research;
- Interact with students and faculty at the poster session;
- Participate in a joint Roadmapping Working Group meeting.
Please note that we have opened the research portion of the
first day to all Working Group members and Invited Guests
- we hope you can join us for both days.
The May 4th Working Group meeting will be "open",
meaning that this is a unique opportunity for you to join
in and participate in up to two different WG sessions at this
conference. A short description of each Working Group is included
below.
Photonics & Roadmapping Spring Conference 2004
Massachusetts Institute of Technology | Cambridge, Massachusetts
May 3rd 2004 – Monday
Photonics Research at MIT
Location: MIT, Bldg 36, 4th Floor (Rm 428), RLE Conference
Room and Lobby 13 (poster session & reception)
| 1:15
PM |
Welcome
and Introductions, Rajeev Ram |
| 1:30-4:30
pm |
Photonics
Research Presentations |
| 1:30pm |
- "Integrated Optoelectronic Fibers", Yoel
Fink, Dept of Materials Science and Engineering
|
| 2:00pm |
|
| 2:30pm |
|
| 3:00pm |
- "Overview of Circuits and Systems in MTL",
Anantha Chandrakasan, Electrical Engineering and Computer
Science
|
| 3:30pm |
|
| 4:00pm |
- Ultrafast All-Optical Networks," Scott Hamilton,
MIT Lincoln Labs
|
| 4:30-6:30
pm |
Poster
Session & Reception |
May 4th, 2004 - Tuesday
Roadmapping Working Group Sessions
Location: MIT, Bldg 36, 4th Floor (Rm 428), RLE Conference
Room
Summary of the CTR Working Groups that
plan to meet on May 4, 2004 at MIT:
"Next Generation Transceivers:
Applications, Markets, and Economics" (NGT WG)
WG Chair: Michael Schabel, Bell Labs, Lucent
The NGT WG will develop a strategic roadmap which elucidates
opportunities to drive convergence of next-generation optoelectronic
components across multiple segments of the communications
industry. This WG will:
- identify targets for next generation
transceivers
- identify opportunities for convergence,
- investigate expansion of total addressable
market (beyond telecommunications applications),
- develop a barrier analysis to driving
convergence in the OE industry,
- develop an action plan.
"High Performance Transceivers"
(HPT WG)
WG Chair: Dominic Goodwill, Nortel Networks
The HPT WG will focus on roadmapping high performance transceivers
with the goal of increasing design re-use, process re-use,
and manufacturing economies of scale. This group will examine
the different functions of the high performance transceiver
platform and how they might effectively be integrated in future
transceivers. In 2004, this group will focus on quantifying
the manufacturing and component design impact of new functions
(e.g. wavelength tunability; coding schemes; supervisory channels,
etc). This WG will consider the feasibility of implementing
these new features over a 5-10 year time period and will attempt
to set realistic timeframes for integration.
"Opto-Electronic Integration
in III-V Materials" (III-V WG)
WG Chair: Prof. Rajeev Ram, Research Lab for Electronics,
MIT
The goal of the III-V WG is to:
- Identify the major drivers for integration
of various electronic and optical functions in III-V materials;
- Develop a comprehensive list of
barriers for large scale monolithic integration;
- Outline viable solutions that can
overcome the barriers and develop a timeline for development
of these technologies.
The III-V WG will work closely with
the Components and Sub-systems WGs to address specific technical
barriers relating to III-V materials. This WG will have an
in-depth understanding of III-V materials, including performance
limitations, device fabrication, and integration challenges.
"Silicon Opto-Electronic
Devices" (Silicon WG)
WG Chair: Jeff Swift, Analog Devices
The charter for the Working Group (WG) on Optoelectronic Integration
in Silicon is to:
- Identify the technical barriers
to large scale optoelectronic circuits in silicon;
- Map out a strategy for integration
of electronic and optical functions;
- Outline the technology alternatives
for overcoming barriers and the time horizons for the alternatives.
The Silicon WG will work closely with
the Components and Sub-systems WGs to address specific technical
barriers relating to Silicon materials. This WG will have
an in-depth understanding of Silicon materials, including
performance limitations, device fabrication, and integration
challenges. This WG will focus on implementing key functions
in silicon (e.g. sources; detectors; modulators) and will
examine critical barriers, such as optical I/O. The WG will
roadmap key functions by assessing performance metrics over
a 10 year time frame. Discussions will include: material augmentation
(including SiGe, BaTiO3) and manufacturing using CMOS foundry
services.
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